Combined Multiplication and Sum-of-Squares Units

Multiplication and squaring are important operations in digital signal processing and multimedia applications. This paper presents designs for units that implement either multiplication, A × B, or sum-of-squares computations, A2 + B2, based on an input control signal. Compared to conventional parallel multipliers, these units have a modest increase in area and delay, but allow either multiplication or sum-of-squares computations to be performed. Combined multiplication and sum-of-squares units for unsigned and two’s complement operands are presented, along with integrated designs that can operate on either unsigned or two’s complement operands. The designs can also be extended to work with a third accumulator operand to compute either Z +A×B or Z +A2 +B2. Synthesis results indicate that a combined multiplication and sum-of-squares unit for 32-bit two’s complement operands can be implemented with roughly 15% more area and nearly the same worst case delay as a conventional 32-bit two’s complement multiplier. 1: Introduction Sum-of-squares computations are found in many digital signal processing (DSP) and multimedia applications including adaptive filtering [1], image compression [2], Euclidean branch calculation [3], pattern recognition [4], equalization [5], vector normalization, and Viterbi coding [6]. Sum-of-squares computations typically take either the two operand form, SS = A +B , (1) or the vector form, SSV = n−1 ∑ i=0 Ai , (2) which is commonly used in mean-square-error calculations. Due to the abundance of sum-of-squares calculations in DSP and multimedia applications, many processors including Texas Instruments’ TMS320C2x and TMS320C55x, DSP Group’s PineDSPCore and OakDSPCore, and Analog Device’s ADSP-218x, provide square and/or square-and-accumulate instructions [7, 8, 9]. These processors use an existing multiplier or multiply-and-accumulate (MAC) unit to perform a single square operation, A2, Proceedings of the Application-Specific Systems, Architectures, and Processors (ASAP’03) ISBN0-7695-1992-X/03 $17.00 © 2003 IEEE or square-and-accumulate operation, Z + A2. On these processors, which provide indirect memory addressing, square and square-and-accumulate instructions are useful because they require less memory bandwidth than multiply and multiply-and-accumulate instructions. Previous research on squaring has mainly focussed on designs for dedicated squarers, which compute the square of an operand [1] [6], [10] [21]. This previous research demonstrates that dedicated parallel squarers can be implemented with roughly half as much hardware and less delay than parallel multipliers. Dedicated squarers work well for nonprogrammable processor designs in which the relative frequency of squaring operations is known in advance. They are, however, less suitable for programmable digital signal processors and multimedia processors, in which the frequency of squaring operations is application dependent. Consequently, for applications that do not frequently perform squaring operations, the extra hardware needed for dedicated squarers goes unused. This paper introduces designs for combined multiplication and sum-of-squares units (CMSSUs). The CMSSUs perform either a multiplication, A × B, or a sum-of-squares computation, A2 +B2, based on an input control signal, s. The CMSSUs use conventional multiplier hardware, plus a modest amount of additional hardware. Thus, they require much less area than a dedicated squarer plus a multiplier. The CMSSUs have an additional advantage over dedicated squarers in that they allow two squares and their summation to be performed as a single operation, which has the potential to improve performance and power consumption. The remainder of this paper is organized as follows. Sections 2 and 3 present designs for CMSSUs for unsigned and two’s complement operands, respectively. Section 4 describes designs for integrated CMSSUs that operate on either unsigned or two’s complement operands, based on a second input control signal, t. Section 5 provides area and delay estimates for the CMSSUs and compares them to estimates for conventional tree multipliers for various operand sizes. Section 6 gives conclusions. The designs presented in this paper assume the input operands are n-bit integer operands, but they can easily be extended to other types of fixed-point operands. 2: Unsigned CMSSUs Two n-bit unsigned binary integers, A = an−1an−2 . . . a1a0, and B = bn−1bn−2 . . . b1b0, have the values A = n−1 ∑ i=0 ai2 and B = n−1 ∑ j=0 bj2 . (3) Their product, A · B, has the value A · B = n−1 ∑ i=0 n−1 ∑ j=0 aibj2 . (4) In developing the designs for the CMSSUs, it is useful to rewrite (4) as A ·B = n−1 ∑ i=0 aibi2 + n−1 ∑ i=1 i−1 ∑ j=0 (aibj + ajbi)2 . (5) Figure 1 shows the partial product matrix for A · B with n = 8. The first summation in (5) corresponds to partial product bits on the anti-diagonal, which has been marked Proceedings of the Application-Specific Systems, Architectures, and Processors (ASAP’03) ISBN0-7695-1992-X/03 $17.00 © 2003 IEEE 2 11 0 2 2 6 2 8 2 7 2 15 2 9 2 12 2 13 2 14 2 10 1 2 2 2 3 4 2 5 2 2 b4 a0 b4 a5 b4 a4 4 a3 b4 a2 b4 a1 b5 a0 b5 5 b5 a4 b5 a3 b5 a2 5 a1 b7 a0 b7 a6 b7 a5 b7 a4 a b 3 b7 a2 b7 b 7 a a1 b6 a0 b6 a6 b6 a5 b6 a4 b6 a3 b6 a2 b6 a1 b1 a0 b1 a1 b2 a0 b 2 b a0 0 a2 b 1 a 0 a7 b0 a6 b0 a5 b0 a4 b0 a3 b0 a2 0 a5 b1 a4 b1 a3 b1 a2 b1 a5 b2 a4 b2 a3 b2 a1 b3 a0 b3 a5 b3 a3 b3 a2 b3 a7 b7 a7 b6 a7 b5 a7 b4 a7 b3 a7 b2 a7 b1 a6 b5 a6 b4 a6 b a6 b2 a6 b1 b b b